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Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages. 

High flexibility, infinite reconfigurability, and fast design-to-market of FPGAs make them a promising platform for modern applications, such as IoT, medical, and automotive applications. Energy and area limitations are challenging in these applications since many of these applications have limited power and hardware resources. Accordingly, the energy- and area-efficient design of FPGAs is of great importance. In this paper, an adiabatic non-volatile hybrid CMOS/MT J logic-in-memory-based configurable logic block (CLB) has been proposed and compared to its state-of-the-art counterparts. The simulation results show that the proposed design has 98%, 98%, 97%, 97%, 96%, and 92 % lower energy consumption compared to CMOS counterparts for frequencies of 1, 2.5, 5,10,20, and 40 MHz. Also, compared to its adiabatic counterparts, the proposed design has at least 74%, 70%, 69%, 69%, and 46% lower energy consumption for frequencies of 1, 2.5, 5, 10, and 20 MHz, respectively. Also, the proposed design has at least 74% fewer transistors compared to its counterparts. Furthermore, the energy saving of the proposed design for different tunnel magnetoresistance (TMR) is almost consistent. In addition, the proposed design keeps its superiority in energy saving over its counterparts for different power supply voltages. 

Energy efficiency and security against side-channel attacks (like power analysis attacks) in modern and battery-operated applications like IoT and medical applications are vital. On the other hand, FPGAs are widely used as a hardware platform for these applications. Accordingly, energy-efficient and power analysis attack-resilient design for FPGA is required. This paper proposes an energy-efficient power analysis attack-resilient adiabatic nonvolatile hybrid MTJ/CMOS LiM-based CLB. The simulation results show that the proposed design has 98.72%, 98.72%, 98.69%, 98.61 %, 98.43%, and 98.11 % (at least 84.69%, 84.74%, 84.28%, 83.19%, 80.70%, and 77%) lower energy consumption compared to its CMOS counterpart (adiabatic counterparts) for frequencies of 1, 2.5, 5, 10, 20, and 40 MHz, respectively. Also, the proposed design keeps its energy consumption superiority for different TMR and power supply voltages, compared to its counterparts. The NED and NSD values of different designs have been calculated and used as power analysis attack-resiliency metrics. The results show that the proposed design has 1053x and 1628x (at least 23x and 14x) lower NED and NSD values compared to its CMOS counterpart (adiabatic counterparts). Furthermore, the NED and NSD values of the proposed design stay in the same range (10−4) for different frequencies, power supply voltages, and TMR. 

Using binarized neural network (BNN) as an alternative to the conventional convolutional neural network is a promising candidate to answer the demand of using human brain-inspired in applications with limited hardware and power resources, such as biomedical devices, IoT edge sensors, and other battery-operated devices. Using nonvolatile memory elements like MTJ devices in a LiM-based architecture can eliminate the need to access and use external memory which can significantly reduce the power consumption and area overhead. In addition, by using adiabatic-based designs, a significant part of the consumed power can be recovered to the power source which leads to a huge reduction in power consumption which is vital in applications with limited power and hardware resources. In this paper by using nonvolatile MTJ devices in a LiM architecture and using adiabatic-based circuits, an XNOR/XOR synapse and neuron is proposed. The proposed design offers 97% improvement in comparison with its state-of-the-art counterparts in case of power consumption. Also, it achieves at least 7% lower area compared to other counterparts which makes the proposed design a promising candidate for hardware implementation of BNNs.